Semiconductor device

ABSTRACT

A semiconductor device comprises a semiconductor substrate that is provided with an integrated circuit; a multi-layered member that is installed in the semiconductor substrate, including a plurality of conductive members and an insulation member; and an external terminal formed on a part of the surface of the multi-layered member. A pair of the conductive members contacts with the upper surface and the lower surface of the insulation member directly under the external terminal, includes a portion where the conductive members are overlapped each other, and are electrically coupled to each other.

RELATED APPLICATIONS

This application claims priority to Japanese Patent Application No.2004-163010 filed Jun. 1, 2004 which is hereby expressly incorporated byreference herein in its entirety.

BACKGROUND

1. Technical Field

The present invention relates a semiconductor device.

2. Related Art

A semiconductor device includes multi-layered structure including anelectrical conductor and an insulation member. An insulation memberprevents electrical conduction among conductors having differentpotentials, being required as holding the insulation property, but it isdifficult to attain it by the conventional technology.

The present invention is intended to prevent electrical conduction amongconductors having different potentials.

SUMMARY

A semiconductor device of the present invention comprises: asemiconductor substrate that is provided with an integrated circuit; amulti-layered member that is formed on the semiconductor substrate,including a plurality of conductive members and an insulation member; anexternal terminal formed on a part of the surface of the multi-layeredmember.

A pair of the conductive members contacts with the upper surface and thelower surface of the insulation member directly under the externalterminal; includes a portion where the conductive members are overlappedeach other; and are electrically coupled to each other.

According to the invention, there is no substantial problem even ifoverlapped portions of a pair of conductive members are electricallyconducted since they are originally conducted.

A semiconductor device of the present invention comprises: asemiconductor substrate that is provided with an integrated circuit; anmulti-layered member that is formed on the semiconductor substrate,including a plurality of conductive members and an insulation member; anexternal terminal formed on surface of the multi-layered member.

A pair of the conductive members contacts with the upper surface and thelower surface of the insulation member directly under the externalterminal; are electrically disconnected each other; and not overlappedeach other directly under the external terminal. According to theinvention, a pair of the conductive members is not overlapped each otherand uneasy to be conducted each other.

In the semiconductor device, the integrated circuit may include aswitching element that turns the pair of conductive members offelectrically, and a part of the switching element or all of it may belocated directly under the external terminal.

In the semiconductor device, the external terminal may be located on thetop layer of the conductive members and electrically connected and thetop layer of the conductive members may be formed as smaller than aprojected area of the external terminal toward the multi-layered member.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a cross sectional view of a part of a semiconductor device ofthe embodiment.

FIG. 2 is a plan view of a part of a semiconductor device of theembodiment.

FIG. 3 shows an application of the above embodiment shown in FIGS. 1 and2.

FIG. 4 shows a circuit board in which a semiconductor device of theembodiment is mounted.

FIG. 5 shows a semiconductor package device including a substrate inwhich a semiconductor device of the embodiment is mounted.

FIG. 6 shows an electronic module including a substrate in which asemiconductor device of the embodiment is mounted and an electronicpanel in which the substrate is mounted.

FIG. 7 shows electronic equipment having a semiconductor device of theembodiment.

FIG. 8 shows electronic equipment having a semiconductor device of theembodiment.

DETAILED DESCRIPTION

Embodiments of the invention will now be described with reference to theaccompanying drawings.

FIG. 1 shows a cross section of a part of a semiconductor device of theembodiment of the invention and FIG. 2 is a plan view showing a part ofthe semiconductor device of the embodiment of the invention.

A semiconductor device includes a semiconductor substrate 10 such assilicon substrate. The semiconductor substrate 10 may be asemiconductor-crystallized substrate. The semiconductor substrate 10includes doped impurities and shows N-type or P- type. The semiconductorsubstrate 10 may be a semiconductor chip or a wafer. A semiconductorwafer is cut by dicing or scribing to obtain a semiconductor chip.

An integrated circuit 12 shown in FIG. 5 is formed on the semiconductorsubstrate 10. The integrated circuit 12, which is a monolithicintegrated circuit for attaining semiconductor functions, is formed in asemiconductor chip of a semiconductor wafer. The semiconductor circuit12 may include a switching element 20 shown in FIG. 1. The switchingelement 20 may be a part of a protective circuit such as electrostaticshielding circuit or an output driver.

In the present embodiment, the switching element 20 is a metal oxidesemiconductor field effect transistor (MOSFET). The semiconductorsubstrate 10 is provided with a well 22 to form the MOSFET. The well 22shows inversed conductivity against that of the substrate 10. Aplurality of diffused regions 24, 26 and 28 is formed with a specificdistance in the well 22. The diffused regions 24, 26 and 28 areimpurity-doped regions. These impurities are doped by thermal diffusionmethod or ion implantation region. FIG. 1 shows that a pair of diffusedregions 24 and 28 is located as a source region adjacent to the bothsides of diffused region 26 as a drain region. The diffused regions 24,26 and 28 show inversed conductivity against that of the well 24. Aninsulation film 30 such as silicon oxide layer is formed on the well 22.

An electrode 32 called as a gate electrode is formed above the diffusedregions 24 and 26 adjacent each other on the insulation film 30. Anelectrode 34 called as a gate electrode is formed above the diffusedregions 26 and 28 adjacent each other on the insulation film 30. Theelectrodes 32 and 34 are electrically insulated from the diffusedregions 24, 26 and 28 via the insulation film 30. The electrodes 32 and34 are electrically connected each other, not shown in the figure. Theelectrodes 32 and 34 are electrically connected to the other elements ofthe integrated circuit 12 via an outgoing line as shown in FIG. 2.According to the embodiment, the electrodes 32 and 34 are formed withsemiconductor material such as poly silicon by a chemical vapordeposition method or sputtering or may be formed with other materialssuch as metals.

A conductive member 36 such as a drain electrode is formed above thediffused region 26 between a pair of diffused regions 24 and 28. Theconductive member 36 is electrically connected to the diffused region 26via the contact portion. Conductive members 38 and 40 such as a sourceelectrode are formed above a pair of diffused regions 24 and 28 adjacentto the diffused region 26. The conductive members 38 and 40 areelectrically connected to the diffused regions 24 and 28 via the contactportion. The conductive members 38 and 40 are electrically connectedeach other and also connected to the other elements of the integratedcircuit 12 as shown in FIG. 2. The conductive members 38 and 40 are madeof a metal such as aluminum in the embodiment.

The switching element 20 is electrically isolated from other elements bythe element isolation region 42. The element isolation region 42 may beformed by a local oxidation id silicon (LOCOS) method. A thick part ofthe insulation film 30 may be the element isolation region 42. Further,an insulation film 44 may be formed on the insulation member 30.

The switching element 20 turns an electrical connection between theconductive elements 36 and 38 on and off, in response to voltage appliedto the gate electrode 32 and 34. Further, the element 20 turns anelectrical connection between the conductive elements 36 and 40 on andoff. The details of such function is well known as MOSFET function andomitted here.

The insulation member 50 is formed on the conductive members 36, 38 and40. The insulation member 50 covers over the conductive members 36, 38and 40. The conductive members 36, 38 and 40 contacts the lower surfaceof the insulation member 50. The insulation member 50 is made of anelectrically insulating material.

A conductive member 52 is formed on the insulation member 50. Theconductive members 52 contacts the upper surface of the insulationmember 50. The conductive members 52 is made of a metal such as aluminumin the embodiment. The conductive member 52 is pulled out as shown inFIG. 2 and electrically connected to the other elements of theintegrated circuit 12. The configuration of pulling out the conductivemember 52 is not limited to that shown in FIG. 2, but may be a smallrectangular shape such as the conductive member 36 in FIG. 2, or mayinclude a part of the configuration of pulling out the conductive member36.

The conductive member 52 is electrically connected to the conductivemember 36 via the contact portion penetrating the insulation member 50.The conductive member 52 overlaps the conductive member 36. Theconductive member 52 is electrically disconnected from the conductivemember 38 and 40. Electrical disconnection is preformed by the switchingelement 20. The conductive member 52 does not overlap the conductivemembers 38 and 40.

The semiconductor device includes a multi-layered member including aplurality of conductive members such as the conductive members 36, 38,40, and 52 and others not shown in the figure, and a single or pluralinsulation member such as the insulation layer 50 and other insulationlayers not shown in the figure.

A passivation film 54 covers over the conductive member 52 located asthe top layer, except a part of it. The passivation film 54 may be onelayer in the multi-layered member.

The external terminal 60 such as a bump is formed above and/or on theconductive member 52 at the exposed area from the passivation film 54.The conductive member 52 is the top layer of conductive members and theexternal terminal 60 is formed above and/or on the multi-layered member.The external terminal 60 is also formed on the passivation film 54.

FIG. 3 shows an application of the above embodiment. FIG. 3 shows aplurality of conductive members 72 located as top layer of conductivemembers and an external terminal 70 connected to the conductive members72. The plurality of conductive members 72 are electrically disconnectedeach other. Not only the conductive member 72 connected to the externalterminal 70, but the other conductive member 72 connected to the otherexternal terminal 70 are located directly under the external terminal 70(a projected surface of the external terminal 70 to the multi-layeredmember). According to the aspect shown in FIGS. 1 and 2, electricalcontact (exposed portion of the passivation film 54) of the conductivemember 52 with the external terminal 60 is small comparing with aprojected surface of the external terminal 60 to the multi-layeredmember. Hence, conductive member electrically connected to otherelements can be formed by using application in FIG. 3 directly under theexternal terminal 60(a projected surface to a multi-layered member.) Asmodification, the conductive member 72 located under the plurality(three layers for example) of external terminals 70 may be a conductivelayer except a top layer of conductive members or combination of the toplayer and a conductive layer except a top layer.

According to the embodiment, a pair of conductive members such as acombination of the conductive member 36 with 52 or other combination notshown in the figure contacts the upper surface and the lower surface ofone insulation member such as the insulation member 50 directly underthe external terminal 60 (a projected surface of the external terminaltoward the multi-layered member). The conductive members are overlappeddirectly under the external terminal 60 and electrically connected eachother. If insulating capability of the insulation member 50 isdeteriorated, the overlapped portion is more electrically conductivethan the non overlapped portion. However, there is no substantialproblem even if overlapped portions of a pair of conductive members 36and 52 are electrically conducted since they were originally conducted.

According to the embodiment, a pair of conductive members such as acombination of the conductive member 38 with 52, a combination of theconductive member 40 with 52 or other combination not shown in thefigure contacts the upper surface and the lower surface of oneinsulation member such as the insulation member 50 directly under theexternal terminal 60 and electrically disconnected. The all conductivemembers are not overlapped directly under the external terminal 60. Ifinsulating capability of the insulation member 50 is deteriorated, thenon-overlapped portion is less electrically conductive than theoverlapped portion. Therefore, a pair of the conductive member 38 with52, or a pair of the conductive member 40 with 52 electricallydisconnected become less conductive.

In the specification, a conductive member means not only a narrowdefinition comprising only a conductive material such as a metal, butalso a broader definition comprising a non conductive material that canpass electrical current such as a semiconductor and a member formed forpassing electrical current (the electrode 32 and 34 for example), Forexample, if one of electrodes 32 and 34 is combined with one ofconductive members 36, 28 and 40 as a pair of members, this pair is alsoone of the above defined pair of conductive members.

In the embodiment, a part of the switching element 20 or all portions ofit are located directly under the external terminal 60, namely aprojected surface of the external terminal 60 toward a multi-layeredmember.

FIG. 4 shows a circuit board 200 in which the semiconductor device ofthe embodiment of the invention, if the semiconductor substrate 10 is asemiconductor chip, is mounted. The semiconductor substrate is mountedby flip chip bonding, for example and wiring pattern not shown in FIG. 2is formed on the circuit board 200.

FIG. 5 shows a semiconductor package including the semiconductor device100 of the embodiment when the semiconductor substrate 10 is asemiconductor chip and a substrate 300 such as a ceramic substrate or aflexible substrate on which the device is mounted by face-down bondingfor example. The semiconductor package is mounted on the circuit board400.

FIG. 6 shows an electronic module including a substrate 500 in which thesemiconductor device 100 of the present embodiment is mounted when thesemiconductor substrate 10 is a semiconductor chip, and an electronicmodule 600 such as a liquid crystal panel or an electro luminescentpanel in which the substrate 500 is mounted. The semiconductor device100 and the substrate 500 comprise a tape carrier package (TCP).

As electronic equipment having the semiconductor device of the presentembodiment, FIG. 7 shows a note type personal computer 700 and FIG. 8shows a cellar phone 800.

It should be noted that the present invention is not limited to theabove-mentioned embodiments, and various changes and modifications canbe made within the spirit and scope of the invention. For example, thepresent invention includes substantially the same structure (includingthe structure with the same functions, methods, and results and thestructure with the same goals and results) as the structure of theabove-mentioned embodiments. The present invention also includes otherstructures in which non-essential elements of the above-mentionedembodiments are substituted. The present invention also includes thestructures that can achieve the same effects or the same goals as thoseachieved by the above-mentioned embodiments. Moreover, the presentinvention includes other structures in which known methods andtechniques are incorporated into the above-mentioned embodiments.Moreover, the present invention includes structures, which are limitedlyexcluded from any of technical items explained in the above embodiments.Moreover, the present invention includes structures in which any ofwell-known technology are limitedly excluded from the above mentionedembodiments.

1. A semiconductor device comprising: a semiconductor substrate that isprovided with an integrated circuit; a multi-layered member that isformed on the semiconductor substrate, including a plurality ofconductive members and an insulation member; and an external terminalformed on the surface of the multi-layered member; wherein a pair of theconductive members contacts with the upper surface and the lower surfaceof the insulation member directly under the external terminal; includesa portion where the conductive members are overlapped each other; andare electrically coupled to each other.
 2. A semiconductor devicecomprising: a semiconductor substrate that is provided with anintegrated circuit; a multi-layered member that is formed on thesemiconductor substrate, including a plurality of conductive members andan insulation member; an external terminal formed on the surface of themulti-layered member; wherein a pair of the conductive members contactswith the upper surface and the lower surface of the insulation memberdirectly under the external terminal; the conductive members areelectrically disconnected each other and not overlapped each other.
 3. Asemiconductor device according to claim 2, wherein the integratedcircuit includes a switching element that turns the pair of conductivemembers off electrically, and a part of the switching element or all ofit is located directly under the external terminal.
 4. A semiconductordevice according to claim 2, wherein the external terminal is located onthe top layer of the conductive members and electrically connected andthe top layer of the conductive members is formed as smaller than aprojected area of the external terminal toward the multi-layered member.